1. Field of the Invention
This invention relates to a signal acquisition and reception method for a Global Positioning System signal receiver.
2. Description of the Prior Art
Signals transmitted from GPS (Global Positioning System) satellites are available to the public and are transmitted by phase modulating a carder signal at 1,575.42 MHz with navigation information about the orbit of the satellite. The modulated carder is then spread spectrum modulated with a specific C/A code for each satellite. A GPS receiver generates a code synchronized with the C/A code of the particular satellite to demodulate the signal and reproduce the carrier signal so that the navigation information can be decoded.
The navigation information contains orbit data divided into two components with highly accurate ephemeris component and with a comparatively low degree of accuracy almanac component. The ephemeris component is used to calculate the position of the satellite accurately, and the almanac component is used to calculate the general area where the satellite is located.
The ephemeris component with respect to the transmitting satellite is transmitted in the navigation message, while the almanac component providing the general area of location for all available GPS satellites is successively transmitted in units of a frame. Accordingly, if the navigation data is collected for a certain period of time, the almanac data for all available satellites will be obtained.
The frequency of the carrier signal from the GPS satellite fluctuates within a certain range as viewed from the GPS receiver due to a Doppler effect arising from the fact that the satellite is moving at a high speed and also due to a frequency deviation of the reference oscillator in the receiver. Further, before the distance between the receiver and the satellite is known, since the propagation time of a signal is unknown, also the phase of the code by which the signal is multiplied in order to spread spectrum is unknown. Therefore, the receiver must search for the carrier frequency and the code phase of the satellite when the GPS receiver is turned on to acquire the signal of the satellite.
Since GPS satellites are orbiting, they are always moving, as viewed from the receiver. In addition, the number of GPS satellites from which signals can be received at a particular position on the earth's surface varies depending upon the orbits of the satellites, the position of the GPS receiver, and the instant in time when the GPS receiver is searching for a satellite. Accordingly, in order to reduce the time required to acquire a signal of a satellite from the initial operation of the GPS receiver, calculation of the orbits of satellites is performed using the almanac component of the satellite, a rough position of the GPS receiver at that particular instant in time is calculated, and those satellites from which signals can be received are set as objects of the initial search.
To this end, in conventional receivers, when power to the receiver is cut, almanac data collected and position data of the receiver measured during the previous reception cycle are stored in memory with battery backup, or in non-volatile memory such as an EEPROM, bubble memory, or flash-RAM, rot the like, and the time is kept by a clock circuit which also operates with battery backup.
Synchronous tracking of a carrier signal is performed by means of a Costas loop, and to this end an I register, a Q register, and a carrier signal generation circuit are provided. Synchronous tracking of a C/A code is performed by means of a DLL (delay lock loop), and to this end, an E register, and L register, and a C/A code generation circuit are provided. Further, in order to acquire a signal and to control the synchronous tracking operation to calculate the position of the GPS receiver, a control calculation circuit including a CPU, a ROM, and RAM are provided.
When a signal is to be acquired, a carrier signal and a C/A code are generated in the GPS receiver and supplied to the I and Q registers to obtain a correlation to the received signal. A peak of the correlation is searched for and obtained by changing the frequency of the generated carrier signal and the phase of the C/A code, so that the object satellite can be acquired.
After the signal is acquired, the difference in phase between the received signal and the generated carrier signal is measured using the I and Q registers, and the carrier signal generation circuit is controlled in response to the phase difference to effect synchronous tracking of the carrier component of the reception signal. Simultaneously, the difference in phase between the received signal and the generated C/A code is measured using the E and L registers, and the code generation circuit is controlled in response to the phase difference to synchronously track the C/A code component of the received signal.
The CPU calculates a value corresponding to the distance between the satellite and the GPS receiver including an error caused by the clock of the receiver, referred to as the pseudorange from the phase of the code being synchronously tracked. The CPU collects such pseudoranges and navigation information of the four satellites, calculates the precise distance from each of the satellites' position using the four pseudoranges and the ephemeris data, and computes the accurate position of the GPS receiver including the latitude, longitude, and altitude, and a displacement of the clock of the receiver from the accurately controlled GPS reference time.
A radio frequency circuit, hereinafter referred to as an RF circuit, and a signal processing circuit of a conventional GPS receiver as described above are described below with reference to FIG. 3 and FIG. 4 respectively, with the RF circuit shown in FIG. 3 described first.
Referring to FIG. 3, a radio wave from a GPS satellite is initially received by an antenna 1, and then amplified by a low noise amplifier (LNA) 2, whereafter it is mixed with an output of a local oscillator (LO) 4 by a mixer 3 so that it is converted into a signal of an intermediate frequency (IF). The IF signal is passed through an IF band pass filter (IF-BPF) 5 to remove undesirable noise from the signal, and is then amplified by an IF amplifier (AMP) 6. The output signal of the IF amplifier 6 is quantized by one bit quantization by a limiter 7 in order to allow the following signal processing to be performed digitally. Finally, the quantized signal is output as an IF signal to the signal processing circuit of FIG. 4.
A reference oscillator 8 supplies a reference frequency signal to the local oscillator and to the signal processing circuit of FIG. 4. The local oscillator 4 forms a PLL (Phase Locked Loop) circuit based on the reference frequency signal and generates a local signal for converting the GPS signal from the satellite into an intermediate frequency signal.
Referring to FIG. 4, an IF signal is input to the signal processing circuit and compared with a code signal received from the code generation circuit 12 by an EXOR (exclusive-OR) circuit 11 to remove the code component from the IF signal. The resulting signal is supplied to the UP terminals of an I counter 13 and a Q counter 14.
The I counter 13 and the Q counter 14 are synchronous bi-directional counters. Both the I counter 13 and the Q counter 14 count in response to the rising edge of a clock signal received at the CK terminal of the respective counter. The counter increments when the UP terminal is set to 37 1" and decrements when the UP terminal is set to "0".
A carrier signal generation circuit 15 generates clock signals ICK and QCK at a predetermined frequency set by the CPU 16. The clock signals ICK and QCK have phases out of phase by 90 degrees from each other and are supplied to the CK terminals of the I counter 13 and the Q counter 14 respectively.
The count values of the I counter 13 and the Q counter 14 are initially stored in an I register 17 and a Q register 18 respectively, and then transferred to the CPU 16 by a data bus. The CPU 16 measures, upon synchronous tracking of a signal, the phase difference of the IF signal from the clock signals ICK and QCK output from the carrier generation circuit 15 using the values of the I register and the Q register. After the signal has been acquired, the value of, for example, I.sup.2 +Q.sup.2 is calculated to measure the intensity of the reception signal.
The code generation circuit 12 generates a CODE signal synchronized with a code component included in the reception signal, and EARLY signal advanced in phase by 0.5 chips to the CODE signal and a LATE signal delayed in phase by 0.5 chips from the CODE signal. Contents of the CODE signal are set by the CPU 16 to coincide with a C/A code of a satellite from which a signal is desired to be received.
The phases of the CODE signal, the EARLY signal, and the LATE signal can be advanced or delayed by a suitable magnitude by the CPU 16. The code generation circuit 12 also produces an EPOCH signal which serves as a reference signal to control the counters and registers having a value of "1" at the top of every CODE signal cycle. The EPOCH signal is synchronized with the CODE signal and supplied to the counter control circuit 19 and the CPU 16.
The carder signal is removed from the IF signal by performing an exclusive-or function using the EXOR circuit 20 on the carrier signal and the clock signal QCK from the carrier generation circuit 15. The IF signal is then compared with the EARLY signal and the LATE signal from the code generation circuit 12 by a pair of EXOR circuits 21 and 22, respectively. The output signals of the EXOR circuits 21 and 22 are input to UP terminals of an E counter 23 and an L counter 24, respectively, so that they are counted up or down in response to a clock signal ELCK from a clock generation circuit 27.
The count values of the E and L counters 23 and 24 are first stored in an E register 25 and an L register 26, respectively, and then transferred to the CPU 16 by a data bus. The values of the E register 25 and the L register 26 indicate the degree of correlation between the IF signal and the EARLY signal and the degree of correlation between the IF signal and the LATE signal, respectively. The CPU 16 calculates, upon synchronous tracking of the C/A code, the difference between the value of the E register and value of the L register, and calculates, from the value of the difference, the difference in phase between the CODE signal output from the code generation circuit 12 and the code component included in the IF signal.
Each of the four counters 13, 14, 23, and 24 have an EN (enable) terminal and a CL (clear) terminal for controlling the counting operation of the counter. The EN terminal enables the counting operation of the counter when it receives "1", and disables the counting operation when it receives "0". The count value of the counter is cleared to zero on the rising edge of the clock signal when the CL terminal is set to "1". When the CL terminal is set to "0", the value of the counter is not cleared.
Each of the four registers 17, 18, 25, and 26 fetch, when the input to an LD (load) terminal of the corresponding register is set to "1", the value at the input terminal Dn of that register. Even if the input to the Dn terminal changes after a value has been input into the register, the value in the register remains the same and is output a Qn terminal of the register until the LD terminal rises again.
The counter control circuit 19 outputs an enable signal EN and a clear signal CL for the counters and a load signal LD for the registers with reference to the EPOCH signal supplied to the counter control circuit 19 from the code generation circuit 12. Each counter performs an accumulation operation for one period (1 msec) of the C/A code by repeating a counting up operation or a counting down operation and transfers its accumulation value (count value) to a respective register.
For example, when the EPOCH signal is generated at the top of a code from the code generation circuit 12, the counter control circuit 19 sets the enable signal EN to "0" to stop operation of the counters and then outputs a load signal LD to cause the values accumulated in the counters up until that time to be read into the respective registers.
After the values accumulated in the counters up until that time are transferred from the counters to the registers in the manner described above, the counter control circuit 19 outputs a clear signal CL to clear the contents of the counters to zero and then returns the enable signal EN to "1" to resume counting operations of the counters to commence the accumulation operation for another period of the C/A code again.
The clock generation circuit 27 produces, based on a reference clock signal supplied clock generation circuit 27 from the reference oscillator 8 of the RF circuit in FIG. 3, clock signals MCK and ELCK to be supplied to the relevant components of the signal processing circuit. In particular, the clock generation circuit 27 supplies a master clock signal MCK which acts as a reference for the operation to the code generation circuit 12, the carrier generation circuit 15, and the counter control circuit 19. Another clock signal ELCK with a predetermined frequency is supplied to the E counter 23 and the L counter 24.
The CPU 16 executes a control program for the receiver held in the ROM 28 making use of RAM 29. The EPOCH signal is input to an interrupt terminal INT of the CPU 16, and in response to the EPOCH signal, an interrupt process is commenced. The values stored in the registers are read into the CPU 16 synchronously along with the EPOCH signal.
Before a signal of a satellite is acquired, the CPU 16 controls the carrier generation circuit 15 and the code generation circuit 12 to search a carrier frequency and a code phase respectively. The search range for the carrier frequency depends upon the Doppler frequency range of the satellite and a frequency deviation of the reference oscillator 8 in the receiver. The search range for the code phase is one period (1,023 chips) of the code.
During searching, the CPU 16 supervises the magnitude of the correlation while successively changing the phase of the code one by one chip at a certain carrier frequency. After the searching for 1,023 chips is completed, the carrier frequency is shifted by a suitable frequency width. Then, at the new carrier frequency position, searching for the code phase is repeated again.
Discovery of one correlation normally requires 1 msec, corresponding to the length of one period of the code. Accordingly, searching the entire range to be searched for the frequency and phase requires a time of: EQU (total number of steps for a frequency).times.1,023.times.1 msec
The CPU 16 calculates, from the values of the I and Q registers 17 and 18, a value which makes an index to the correlation such as, for example, I.sup.2 +Q.sup.2 or .vertline.I.vertline.+.vertline.Q.vertline.. When the value calculated exceeds a certain threshold value, the CPU 16 determines that the signal of the satellite is received and ends the searching operation. Thereafter, the CPU 16 enters a signal tracking operation.
Upon synchronous tracking of a signal, the CPU 16 calculates, from the values of the I and Q registers 17 and 18, a value corresponding to the phase difference between the reception signal and the carrier signal generated by the carrier generation circuit 15, and applies calculation of a loop filter to the value. Then, the CPU 16 controls the carrier generation circuit 15 in accordance with a result of the calculation so that the frequency of the carrier may track the reception signal. Simultaneously, the CPU 16 calculates, from the values of the E and L registers 25 and 26, the phase difference between the reception signal and the code generated by the code generation circuit 12 and applies calculation of a loop filter to the value. Then, the CPU 16 controls, in accordance with a result of the calculation, the code generation circuit 12 so that the phase of the code may track the reception signal.
While acquisition and synchronous tracking of a signal are performed in such a manner as described above, a receiver, which includes only one such signal processing circuit of FIG. 4, successively changes over the satellite for reception in a time-dividing condition to perform measurement of a pseudorange and collection of the navigation message for four satellites. On the other hand, another receiver, which includes four or more such signal processing circuits, can obtain pseudoranges and navigation messages while receiving signals from four satellites at a time. The CPU 16 thus performs calculation for position measurement to find out the current position of the receiver when pseudoranges and ephemeris data of four satellites are collected.
During operation of the receiver, the current position obtained by the position fix and the almanac data of the satellites are normally written into RAM 29. The RAM 29 consists of a RAM of the static type whose stored contents are held using a backup battery. While the power source to the receiver is interrupted, power is supplied from a battery 32 to the RAM 29 and the clock circuit (RTC) 30 by way of a power source switching circuit 31 so as to hold the contents of the RAM 29 and maintain a time counting operation of the clock circuit 30.
The clock circuit 30 includes a quartz oscillator and a counter (not shown) therein and always keeps the current time since it is backed up by the battery 32. The CPU 16 calibrates thee time of the clock circuit 30 when an accurate current time is obtained as a result of calculation for a position fix.
When a satellite is to be acquired first after the power source to the receiver is turned on, in order to reduce the time before acquisition, calculation for an orbit is performed based on position data of the receiver and almanac data of the satellites held in the RAM 29 and the current time maintained in the clock circuit 30 to find the rough positions of the satellites, and one of the satellites from which a signal can be received at the point of time is selected as an object for acquisition.
In the conventional signal processing circuit described above, since a satellite from which a signal can be received at a current point of time is selected as an object for acquisition based on calculation for an orbit after the power source to the receiver is turned on, almanac data collected during preceding reception, position information obtained by the last position fix, and the current time must be held also while the power source to the receiver is interrupted. Therefore, the expensive clock circuit 30 for counting the time and the battery 32 for backing up the clock circuit 30 and the RAM 39 are essential and required.
Further, it is another drawback of the conventional signal processing circuit in that, when data of the RAM 29 are destroyed by some cause while the power source is interrupted or where the receiver has not been used for such a long time that almanac data held in the RAM 29 become so old that they cannot be relied upon any more, a longer time than usual is required before acquisition of a signal of a satellite after turning on the power source, and consequently, operation of the receiver is not invariable and the reliability is low.